Make itself does not compile the source files. The Makefile (input for make) contains a set of targets. Each target has a set of dependencies (on other targets) and rules how to build the target. Make reads the Makefile(s) and manages all targets, dependencies, and build rules.

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In the former Makefile, a is not evaluated until it’s used elsewhere in the Makefile, while in the latter a is evaluated immediately even though it’s not used. This is an old question but this example helps me understand the difference whenever I forget. On Windows 10 or Windows 11, you can run the command winget install ezwinports.make in the command line or PowerShell to quickly install it, restart the command line or PowerShell. An outdated alternative was MinGW, but the project seems to be abandoned, so it’s better to go for one of the previous choices. Find centralized, trusted content and collaborate around the technologies you use most.

make: *** Error 1 error duplicate

You can either set -j or even higher -j so that compilation can happen in parallel. All relative paths in the makefile will be relative to your current directory and not the directory of the makefile. I’m following the instructions of someone whose repository I cloned to my machine. I want to use the make command as part of setting up the code environment, but I’m using Windows. Connect and share knowledge within a single location that is structured and easy to search.

Since a thread that does disk operations is technically almost idle from CPU point of view, add one to the total number of cores. As you say the -j flag tells make that it is allowed to spawn the provided amount of ‘threads’. Ideally each thread is executed on its own core/CPU, so your multi-core/CPU environment is used to its fullest. Can I pass variables to a GNU Makefile as command line arguments? In other words, I want to pass some arguments which will eventually become variables in the Makefile. So in order to attack the problem, the error message from gcc is required.

Specifying path to “makefile” using “make” command

If it’s from Linux, you might need to use a real Linux or WSL. If make can run parallel builds, it will launch up to 6 simultaneous compilation process (e.g. 6 calls to gcc). The -j option is only use to speed up application build, it determines how many jobs make can spawn for the build.

How can I pass a macro definition from “make” command line arguments (-D) to C source code?

Then in your makefile you can refer to $(foo). Note that this won’t propagate to sub-makes automatically. To add or update packages, just run the setup again and select the desired package versions. In my case there was a static variable which was not initialized. I don’t plinko slot know the logic behind it but worked for me.